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1/30 semiconductor MSM56V16160F 2-bank 524,288 word 16 bit synchronous dynamic ram description the MSM56V16160F is a 2-bank 524,288-word 16 bit synchronous dynamic ram, fabricated in okis cmos silicon-gate process technology. the device operates at 3.3v. the inputs and outputs are lvttl compatible. features silicon gate , quadruple polysilicon cmos , 1-transistor memory cell 2-bank 524,288-word 16bit configuration 3.3v power supply 0.3v tolerance input : lvttl compatible output : lvttl compatible refresh : 4096 cycles/64 ms programmable data transfer mode - cas latency (1,2,3) - burst length (1,2,4,8,full page) - data scramble (sequential , interleave) cbr auto-refresh, self-refresh capability package: 50-pin 400mil plastic tsop (type ii) (tsopii50-p-400-0.80-k) (product : MSM56V16160F-xxts-k) xx : indicates speed rank. product family access time (max.) family max. frequency t ac2 t ac3 MSM56V16160F-8 125mhz 9ns 6ns MSM56V16160F-10 100mhz 9ns 9ns this version : sep.1999
MSM56V16160F 2/30 pin configration (top view) pin name function pin name function clk system clock udqm, ldqm data input/output mask cs chip select dqi data input/output cke clock enable v cc power supply (3.3v) a0Ca10 address v ss ground (0v) a11 bank select address v cc q data output power supply (3.3v) ras row address strobe v ss q data output ground (0v) cas column address strobe nc no connection we write enable note: the same power supply voltage must be provided to every v cc pin and v cc q pin. the same gnd voltage level must be provided to every v ss pin and v ss q pin. 50-pin plastic tsop ( ii ) (k type) 24 19 20 21 22 23 14 15 16 17 18 7 44 37 36 35 34 33 32 31 30 29 28 27 a11 a10 v ss q v cc qv cc q v ss nc udqm nc a8 a7 a6 we cas ras cs a0 a1 a2 ldqm a5 a4 clk cke 1 2 3 4 5 6 8 9 10 11 12 13 50 49 48 47 46 45 43 42 41 40 39 38 dq1 dq2 v cc v cc q v ss v cc q dq13 dq12 dq11 v ss q dq6 v ss q dq7 dq8 dq3 dq4 dq5 dq10 dq9 dq14 dq16 dq15 v ss q a3 a9 26 25 v cc
MSM56V16160F 3/30 pin description clk fetches all inputs at the h edge. cs disables or enables device operation by asserting or deactivating all inputs except clk, cke, udqm and ldqm. cke masks system clock to deactivate the subsequent clk operation. if cke is deactivated, system clock will be masked so that the subsequent clk operation is deactivated. cke should be asserted at least one cycle prior to a new command. address row & column multiplexed. row address : ra0 C ra10 column address : ca0 C ca7 a11 slects bank to be activated during row address latch time and selects bank for precharge and read/write during column address latch time. a11=l : bank a, a11=h : bank b ras cas we functionality depends on the combination. for details, see the function truth table. udqm, ldqm masks the read data of two clocks later when udqm and ldqm are set h at the h edge of the clock signal. masks the write data of the same clock when udqm and ldqm are set h at the h edge of the clock signal. udqm controls upper byte and ldqm controls lower byte. dqi data inputs/outputs are multiplexed on the same pin.
MSM56V16160F 4/30 block diagram timing register column decoders sense amplifiers dq 1 - dq16 ras cas a 0 - a 11 progra- ming register bank controller latency & burst controller internal col. address counter i/o controller column address buffers internal row address counter row address buffers 8 row decoders row decoders 12 word drivers word drivers 8mb memory cells 8mb memory cells read data register output buffers column decoders sense amplifiers input data register input buffers cke cl k cs we udqm ldqm a 11 8 12 16 16 16 16 16 8
MSM56V16160F 5/30 electrical characteristics absolute maximum ratings (voltages referenced to v ss ) parameter symbol rating unit voltage on any pin relative to v ss v in , v out - 0.5 to v cc + 0.5 v v cc supply voltage v cc , v cc q - 0.5 to 4.6 v storage temperature t stg - 55 to 150 c power dissipation p d * 600 mw short circuit current i os 50 ma operating temperature t opr 0 to 70 c *: ta = 25c recommended operating conditions (voltages referenced to v ss = 0v) parameter symbol min. typ. max. unit power supply voltage v cc , v cc q 3.0 3.3 3.6 v input high voltage v ih 2.0 ? v cc + 0.2 v input low voltage v il - 0.3 ? 0.8 v capacitance (v bias = 1.4v, ta = 25c, f = 1mhz) parameter symbol min. max. unit input capacitance (clk) c clk 2.5 4 pf input capacitance (ras, cas, we, cs, cke, udqm, ldqm, a0-a11) c in 2.5 5 pf input/output capacitance (dq1-dq16) c out 46.5pf
MSM56V16160F 6/30 dc characteristics msm56v16160 condition f-8 f-10 parameter symbol bank cke others min max min max unit note output high voltage v oh ?? i oh = - 2.0ma 2.4 ? 2.4 ? v output low voltage v ol ?? i ol = 2.0ma ? 0.4 ? 0.4 v input leakage current i li ?? ?- 10 10 - 10 10 a input leakage current i lo ?? ?- 10 10 - 10 10 a i cc1 one bank active cke 3 v ih t cc =min. t rc =min. no burst ? 80 ? 70 ma 1,2 average power supply current (operating) i cc1d both banks active cke 3 v ih t cc =min. t rc =min. t rrd =min. no burst ? 115 ? 95 ma 1,2 power supply current (standby) i cc2 both banks precharge cke 3 v ih t cc =min. ? 35 ? 30 ma 3 average power supply current (clock suspension) i cc3s both banks active cke v il t cc =min. ? 3 ? 3ma2 average power supply current (active standby ) i cc3 one bank active cke 3 v ih t cc =min. ? 40 ? 35 ma 3 power supply current (burst) i cc4 both banks active cke 3 v ih t cc =min. ? 125 ? 100 ma 1,2 power supply current (auto-refresh) i cc5 one bank active cke 3 v ih t cc =min. t rc =min. ? 80 ? 70 ma 2 average power supply current (self-refresh) i cc6 both banks precharge cke v il t cc =min. ? 2 ? 2ma average power supply current (power down) i cc7 both banks precharge cke v il t cc =min. ? 2 ? 2ma notes: 1. measured with outputs open. 2. the address and data can be changed once or left unchanged during one cycle. 3. the address and data can be changed once or left unchanged during two cycles.
MSM56V16160F 7/30 mode set address keys cas latency burst type burst length a6 a5 a4 cl a3 bt a2 a1 a0 bt = 0 bt = 1 0 0 0 reserved 0 sequential 0 0 0 1 1 0 0 1 1 1 interleave 0 0 1 2 2 010 2 010 4 4 011 3 011 8 8 1 0 0 reserved 1 0 0 reserved reserved 1 0 1 reserved 1 0 1 reserved reserved 1 1 0 reserved 1 1 0 reserved reserved 1 1 1 reserved 1 1 1 full page reserved notes: a7, a8, a9, a10 and a11 should stay l during mode set cycle. power on sequence 1. with inputs in nop state, turn on the power supply and start the system clock. 2. after the v cc voltage has reached the specified level, pause for 200 m s or more with the input kept in nop state. 3. issue the precharge all bank command. 4. apply a cbr auto-refresh eight or more times. 5. enter the mode register setting command.
MSM56V16160F 8/30 ac characteristic (1/2) note 1,2 msm56v16160 f-8 f-10 parameter symbol min. max. min. max. unit note cl = 3 8 ? 10 ? ns cl = 2 12 ? 15 ? ns clock cycles time cl = 1 t cc 24 ? 30 ? ns cl = 3 ? 6 ? 9ns3,4 cl = 2 ? 9 ? 9ns3,4 access time from clock cl = 1 t ac ? 22 ? 27 ns 3,4 clock high pulse time t ch 3 ? 3 ? ns 4 clock low pulse time t cl 3 ? 3 ? ns 4 input setup time t si 2 ? 3 ? ns input hold time t hi 1 ? 1 ? ns output low impedance time from clock t olz 3 ? 3ns output high impedance time from clock t ohz ? 8 ? 8ns output hold from clock t oh 3 ? 3 ? ns 3 ras cycle time t rc 70 ? 90 ? ns ras precharge time t rp 20 ? 30 ? ns ras active time t ras 48 10 5 60 10 5 ns ras to cas delay time t rcd 20 ? 30 ? ns write recovery time t wr 8 ? 15 ? ns ras to ras bank active delay time t rrd 20 ? 20 ? ns refresh time t ref ? 64 ? 64 ms power-down exit setup time t pde t si +1clk ? t si +1clk ? ns input level transition time t t ? 3 ? 3ns cas to cas delay time(min.) l ccd 11cycle clock disable time from cke l cke 11cycle data output high impedance time from udqm, ldqm l doz 22cycle data input mask time from udqm, ldqm l dod 00cycle data input mask time from write command l dwd 00cycle
MSM56V16160F 9/30 ac characteristic (2/2) note 1,2 msm56v16160 f-8 f-10 parameter symbol min. max. min. max. unit note data output high impedance time from precharge command l roh cl cl cycle active command input time from mode register set command input (min.) l mrd 33cycle write command input time from output l owd 22cycle notes: 1) ac measurements assume that t t = 1ns. 2) the reference level for timing of input signals is 1.4v. 3) output load. 4) the access time is defined at 1.5v. 5) if t t is longer than 1ns, then the reference level for timing of input signals is v ih and v il . output z=50 w 50pf (external load)
MSM56V16160F 10/30 timing waveform read & write cycle (same bank) @cas latency = = = = 2, burst length = = = = 4 t oh ra ca0 t rp t rc qa1 ras cas addr we udqm, ldqm clk cke cs cb0 rb a11 rb ra a10 dq qa0 qa2 qa3 db0 db1 db2 db3 t ac t ohz t wr row active read command precharge command row active write command precharge command t rcd 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
MSM56V16160F 11/30 single bit read-write-read cycle (same page) @cas latency = = = = 2, burst length = = = = 4 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm row active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high t olz db t si qc t hi qa t oh ra l owd bs bs bs bs bs ra cc cb ca t ohz t ac t hi t si t si t hi t hi t si t si t hi t hi t si i ccd t si t cl t cc t ch read command write command read command precharge command
MSM56V16160F 12/30 * notes : 1. when cs is set high at a clock transition from low to high, all inputs except cke, udqm and ldqm are invalid. 2. when issuing an active, read or write command, the bank is selected by a11. a11 active, read or write 0 bank a 1 bank b 3. the auto precharge function is enabled or disabled by the a10 input when the read or write command is issued. a10 a11 operation 0 0 after the end of burst, bank a holds the idle status. 1 0 after the end of burst, bank a is precharged automatically. 0 1 after the end of burst, bank b holds the idle status. 1 1 after the end of burst, bank b is precharged automatically. 4. when issuing a precharge command, the bank to be precharged is selected by the a10 and a11 inputs. a10 a11 operation 0 0 bank a is precharged. 0 1 bank b is precharged. 1 x both banks a and b are precharged. 5. the input data and the write command are latched by the same clock (write latency = 0). 6. the output is forced to high impedance by (1clk+t ohz ) after udqm, ldqm entry.
MSM56V16160F 13/30 page read & write cycle (same bank) @cas latency = = = = 2, burst length = = = = 4 * notes: 1. to write data before a burst read ends, udqm and ldqm should be asserted three cycles prior to the write command to avoid bus contention. 2. to assert row precharge before a burst write ends, wait t wr after the last write data input. input data during the precharge input cycle will be masked internally. clk cke cs ras cas addr a11 a10 dq we udqm, ldqm read command read command write command write command precharge command qa0 qa1 qb0 qb1 dc0 dc1 dd0 cc0 cd0 ca0 cb0 t wr i ccd * * * * note 2 * * * * note 1 bank a active 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 l owd high
MSM56V16160F 14/30 read & write cycle with auto precharge @ burst length = = = = 4 dq we udqm, ldqm row active (a-bank) dq udqm, ldqm dq udqm, ldqm a-bank precharge start clk cke cs ras cas addr a10 a11 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 row active (b-bank) a bank read with auto precharge b bank write with auto precharge b bank precharge start point a-bank precharge start a-bank precharge start hi g h ra t rrd qa0 t wr rb ra rb ca cb qa1 qa2 qa3 db0 db1 db2 db3 db0 db1 db2 db3 qa0 qa1 qa2 qa3 qa0 qa1 qa2 qa3 db0 db1 db2 db3 cas latency=2 cas latency=3 cas latency=1
MSM56V16160F 15/30 bank interleave random row read cycle @cas latency = 2, burst length = 4 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb1 qbb2 qbb3 qbb4 qac0 qac1 qac2 qac3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) read command (b-bank) precharge command (b-bank) row active (a-bank) read command (a-bank) t rrd t rc 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 hi g h
MSM56V16160F 16/30 bank interleave random row write cycle @cas latency = 2, burst length =4 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb rac cac raa rbb rac daa0 daa1 daa2 daa3 row active (a-bank) write command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) precharge command (b-bank) row active (a-bank) write command (a-bank) dbb0 dbb1 dbb2 dbb3 dac0 dac1 high precharge command (a-bank)
MSM56V16160F 17/30 bank interleave page read cycle @cas latency = 2, burst length =4 * note: 1. cs is ignored when ras, cas and we are high at the same cycle. clk cke cs ras cas addr a11 a10 dq we udqm, ldqm 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 raa caa rbb cbb cac cbd cae raa rbb qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qbd0 qbd1 qae0 qae1 * * * * note 1 row active (a-bank) read command (a-bank) row active (b-bank) read command (b-bank) precharge command (a-bank) read command (a-bank) read command (a-bank) read command (b-bank) i roh high
MSM56V16160F 18/30 bank interleave page write cycle @cas latency = 2, burst length = = = = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 we udqm, ldqm row active (a-bank) clk cke cs ras cas addr a10 a11 row active (b-bank) write command (a-bank) precharge command (both bank) hi g h raa caa raa rab rbb cbd dq daa3 dbb0 dbb1 dbb2 dbb3 dac0 dac1 dbd0 write command (b-bank) write command (a-bank) write command (b-bank) daa2 daa1 daa0 cac cbb
MSM56V16160F 19/30 bank interleave random row read/write cycle @cas latency = 2, burst length = 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm raa caa rbb cbb rac cac raa rbb rac qaa0 qaa1 qaa2 qaa3 qbb0 qbb1 qbb2 qbb3 qac0 qac1 qac2 qac3 row active (a-bank) read command (a-bank) precharge command (a-bank) row active (b-bank) write command (b-bank) row active (a-bank) read command (a-bank) hi g h
MSM56V16160F 20/30 bank interleave page read/write cycle @cas latency = 2, burst length =4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm caa0 cbb0 cac0 qaa0 qaa1 qaa2 qaa3 read command (a-bank) write command (b-bank) read command (a-bank) dbb0 dbb1 dbb2 dbb3 qac0 qac1 high qac2 qac3
MSM56V16160F 21/30 clock suspension & dqm operation cycle @cas latency = 2, burst length =4 * notes: 1. when clock suspension is asserted, the next clock cycle is ignored. 2. when ldqm and udqm are asserted, the read data after two clock cycles is masked. 3. when ldqm and udqm are asserted, the write data in the same clock cycle is masked. 4. when ldqm is set high, the input/output data of dq0-7 is masked. when udqm is set high, the input/output data of dq8-15 is masked. clk cke cs ras cas addr a11 a10 dq0-7 we udqm ra ca cb cc ra qa0 qa1 qa2 qb0 qb1 dc0 dc2 * * * * note 1 row active read command clock suspension read dqm clock suspension read command write command read dqm * * * * note 1 * * * * note 2 * * * * note 3 t ohz write dqm write dqm dq8-15 qa0 qa3 qa2 qb0 qb1 dc0 dc1 ldqm t ohz * * * * note 4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 read dqm * * * * note 4
MSM56V16160F 22/30 read to write cycle (same bank) @cas latency = 2, burst length =4 * note: 1. in case cas latency is 3, read can be interrupted by write. the minimum command interval is [burst length + 1] cycles. udqm and ldqm must be high at least 3 clocks prior to the write command. clk cke cs ras cas addr a11 a10 dq we udqm, ldqm ra ca0 cb0 ra db0 db1 * * * * note 1 row active read command write command precharge command t wr t rcd db2 db3 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 da0
MSM56V16160F 23/30 read interruption by precharge command @burst length =8 * notes: 1. when the cas latency = 1, and if row precharge is asserted before a burst read ends, then the read data will not output after the next clock cycle of the precharge command. 2. when the cas latency = 2, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. 3. when the cas latency = 3, and if row precharge is asserted before burst read ends, then the read data will not output after the second clock cycle of the precharge command. dq we udqm, ldqm dq udqm, ldqm cas latency=2 dq udqm, ldqm cas latency=3 clk cke cs ras cas addr a11 a10 ra ca * * * * note 1 qa0 qa1 ra qa2 * * * * note 2 qa3 qa4 qa5 qa0 qa1 qa2 qa3 qa4 qa5 * * * * note 3 qa0 qa1 qa2 qa3 qa4 row active read command precharge command l roh l roh qa5 l roh 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high cas latency=1
MSM56V16160F 24/30 burst stop command @burst length =8 dq we udqm, ldqm dq udqm, ldqm cas latency=2 dq udqm, ldqm cas latency=3 clk cke cs ras cas addr a11 a10 ca qa0 qa1 qa2 qa3 qa4 qa0 qa1 qa2 qa3 qa4 qa0 qa1 qa2 qa3 qa4 cas latency=1 read command cb qb0 qb1 qb2 qb3 qb4 qb0 qb1 qb2 qb3 qb4 qb0 qb1 qb2 qb3 qb4 burst stop command write command burst stop command 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 high
MSM56V16160F 25/30 power down mode @cas latency = 2, burst length =4 * notes: 1. when both banks are in precharge state, and if cke is set low, then the MSM56V16160F enters power-down mode and maintains the mode while cke is low. 2. to release the circuit from power-down mode, cke has to be set high for longer than t pde (t si + 1clk). 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 cke cs ras cas addr a11 a10 dq ra ca ra qa0 qa1 qa2 * * * * note 2 power-down entry row active power-down exit precharge command read command clock suspension exit t si clk * * * * note 1 clock suspension entry t pde t si t si t ref (min.) we udqm, ldqm
MSM56V16160F 26/30 self refresh cycle 0 1 2 clk cke cs ras cas addr a11 a10 dq we udqm, ldqm ra bs ra self refresh entry self refresh exit row active t si t rc hi - z
MSM56V16160F 27/30 mode register set cycle auto refresh cycle dq clk cke cs ras cas addr we udqm, ldqm new command l mrd auto refresh t rc mrs auto refresh key ra 0 1 2 3 4 5 6 9 10 11 0 1 2 3 4 5 6 7 8 hi - z hi - z hi g h hi g h
MSM56V16160F 28/30 function truth table (table 1) (1/2) current state 1 cs ras cas we ba addr action hxxxx xnop lhhhx x nop l h h l ba x illegal 2 lhlxba ca illegal 2 l l h h ba ra row active l l h l ba a10 nop 4 lllhx x auto-refresh or self-refresh 5 idle lllllop codem ode register write hxxxx xnop lhhxx xnop lhlhbaca, a10read l h l l ba ca, a10 write llhhbara illegal 2 l l h l ba a10 precharge row active lllxx xillegal hxxxx xnop (conti nue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 llhhbara illegal 2 l l h l ba a10 term burst, execute row precharge read lllxx xillegal hxxxx xnop (conti nue row active after burst ends) l h h h x x nop (continue row active after burst ends) l h h l x x term burst --> row active l h l h ba ca, a10 term burst, start new burst read 3 l h l l ba ca, a10 term burst, start new burst write 3 llhhbara illegal 2 l l h l ba a10 term burst, execute row precharge 3 write lllxx xillegal hxxxx xnop (conti nue burst to end and enter row prechar g e) l h h h x x nop (continue burst to end and enter row prechar g e) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 read with auto prechar g e lllxx xillegal hxxxx xnop (conti nue burst to end and enter row prechar g e) l h h h x x nop (continue burst to end and enter row prechar g e) l h h l ba x illegal 2 l h l h ba ca, a10 illegal 2 l h l l x x illegal l l h x ba ra, a10 illegal 2 write with auto prechar g e lllxx xillegal
MSM56V16160F 29/30 function truth table (table 1) (2/2) current state 1 cs ras cas we ba addr action hxxxx x nop --> idle after t rp lhhhx x nop --> idle after t rp l h h l ba x illegal 2 lhlxba ca illegal 2 llhhbara illegal 2 l l h l ba a10 nop 4 precharge lllxx xillegal hxxxx xnop lhhhx x nop l h h l ba x illegal 2 lhlxba ca illegal 2 llhhbara illegal 2 l l h l ba a10 illegal 2 write recovery lllxx xillegal hxxxx x nop --> row active after t rcd lhhhx x nop --> row active after t rcd l h h l ba x illegal 2 lhlxba ca illegal 2 llhhbara illegal 2 l l h l ba a10 illegal 2 row active lllxx xillegal hxxxx x nop --> idle after t rc lhhxx x nop --> idle after t rc l h l x x x illegal l l h x x x illegal refresh lllxx xillegal hxxxx xnop lhhhx x nop l h h l x x illegal l h l x x x illegal mode re g ister access l lxxx xillegal abbreviations ra = row address ba = bank address nop = no operation command ca = column address ap = auto precharge * notes : 1. all inputs are enabled when cke is set high for at least 1 cycle prior to the inputs. 2. illegal to bank in specified state, but may be legal in some cases depending on the state of bank selection. 3. satisfy the timing of l ccd and t wr to prevent bus contention. 4. nop to bank precharging or in idle state. precharges activated bank by ba or a10. 5. illegal if any bank is not idle.
MSM56V16160F 30/30 function truth table for cke (table 2) current state (n) cken-1 cken cs ras cas we addr action h x x x x x x invalid l h h x x x x exit self refresh --> abi l h l h h h x exit self refresh --> abi l h l h h l x illegal l h l h l x x illegal l h l l x x x illegal self refresh l l x x x x x nop (maintain self refresh) h x x x x x x invalid l h h x x x x exit power down --> abi l h l h h h x exit power down --> abi l h l h h l x illegal l h l h l x x illegal lhllxxx illegal 6 power down l l x x x x x nop (continue power down mode) h h x x x x x refer to table 1 h l h x x x x enter power down h l l h h h x enter power down h l l h h l x illegal h l l h l x x illegal h l l l h l x illegal h l l l l h x enter self refresh h l llll xillegal all banks idle 6 (abi) l l xxxx xnop h h x x x x x refer to operations in table 1 h l x x x x x begin clock suspend next cycle l h x x x x x enable clock of next cycle any state other than listed above l l x x x x x continue clock suspension * notes : 6. power-down and self-refresh can be entered only when all the banks are in an idle state.
no tic e 1. the information contained herein can change without notice owing to product and/or technical improvements. before using the product, please make sure that the information being referred to is up-to-date. 2. the outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. when planning to use the product, please ensure that the external conditions are reflected in the actual circuit and assembly designs. 3. when designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. 4. oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. 5. neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or information and drawings contained herein. no responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. 6. the products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). these products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. such applications include, but are not limited to:traffic control, automotive, safety, aerospace, nuclear power control, and medical, including lift support and maintenance. 7. certain products in this document may need government approval before they can be exported to particular countries. the purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. 8. no part of the contents contained herein may be reprinted or reproduced without our prior permission. copyright 199 7 oki electric industry co.,ltd.

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